1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a capacitor of a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
Semiconductor devices include unit cells. A unit cell of a DRAM device consists of a cell capacitor and an access transistor. The cell capacitor directly affects the characteristics of the DRAM device. As the cell capacitance increases, a soft error rate (SER) is reduced and a low voltage operation characteristic is improved. However, as the circuit integration density of the DRAM device increases, the area occupied by the unit cell is reduced. Accordingly, in order to improve the reliability and the electrical characteristics of a highly integrated DRAM device, a cell capacitor having a capacitance larger than a certain value must be fabricated within the restricted area size of the DRAM device.
Recently, in order to increase the cell capacitance, a material layer having a high dielectric constant, such as a tantalum oxide (Ta2O5) layer, an aluminum oxide (Al2O3) layer, a barium, strontium and titanium (BST) layer ((Ba,Sr)TiO3), a lead, zirconium, and titanium (PZT) layer ((Pb,Zr)TiO3), or a lead, lanthanum, zirconium, and titanium (PLZT) layer ((Pb,La,Zr)TiO3), was adopted as a dielectric layer interposed between a storage electrode and a plate electrode in order to increase the cell capacitance. However, a high dielectric layer such as either the Ta2O5 layer, the BST layer, the PZT layer, or the PLZT layer must be deposited by a sputtering process, an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process and thermally treated at a temperature of about 550xc2x0 C. to 750xc2x0 C. When the storage electrode is formed of a polysilicon layer, the storage electrode is oxidized. Accordingly, the thickness of the dielectric layer increases or an intersurface characteristic between the dielectric layer and the storage electrode deteriorates, thus deteriorating the leakage current characteristic of the dielectric layer. Therefore, the storage electrode of a capacitor employing the high dielectric layer having the high dielectric constant must be formed from an oxidation-resistant metal layer or a metal oxide layer having excellent conductivity. A platinum (Pt) layer is widely used as the oxidation-resistant metal layer. A ruthenium oxide (RuO2) layer is widely used as the metal oxide layer having excellent conductivity. The storage electrode is preferably manufactured to have a three-dimensional shape, for example, the storage electrode may be cylindrical in order to increase the capacitance of the capacitor formed within the size restricted cell area.
FIGS. 1 through 3 are sectional views describing a method for manufacturing a conventional cylindrical capacitor. As shown in FIG. 1, an interlayer dielectric layer is formed on a semiconductor substrate 1. An interlayer dielectric layer pattern 3, including a storage node contact hole which exposes a predetermined region of the semiconductor substrate 1, is formed by patterning the interlayer dielectric layer. A contact plug 5, which contacts the semiconductor substrate 1, is formed from a conductive material such as tungsten (W) and is placed in the storage node contact hole.
Referring to FIG. 2, a sacrificial insulating layer 7 is formed on the entire surface of the semiconductor substrate. The sacrificial insulating layer pattern 7 includes a hole exposing the contact plug 5. A conductive layer 9 is formed over the entire surface of the semiconductor substrate over the sacrificial insulating layer pattern 7. The conductive layer 9 is made from an oxidation-resistant metal layer, such as a platinum (Pt) layer, or a conductive metal oxide layer, such as a ruthenium oxide (RuO2) layer.
Currently, the oxidation-resistant metal layer and the conductive metal oxide layer are difficult to form using a chemical vapor deposition (CVD) method. Accordingly, the conductive layer 9 is generally formed by a well-known sputtering method. However, the sputtering process show problems associated with poor step coverage. As a result, the thickness T2 of the conductive layer 9 as formed on the side wall of the sacrificial insulating layer pattern 7, is less than the thickness of TI, where the conductive layer 9 is formed on an upper surface of the sacrificial insulating layer pattern 7. Efforts to increase the thickness of T2 using the sputtering method renders the thickness T1 to become very thick. Since the cost of the material layer used for the conductive layer 9 is high, the manufacturing cost of the semiconductor device increases with the use of thicker material layers. Therefore, it is difficult and expensive to increase the thickness of the conductive layer 9 formed on the side wall of the sacrificial insulating layer pattern 7 using traditional sputtering methods. Also, shown in FIG. 2 is an insulating layer 11 for planarization. The insulating layer 11 for planarization fills a concave region on the contact plug 5. The insulating layer 11 for planarization may be a CVD oxide layer which is formed over the entire surface of the semiconductor substrate over the conductive layer 9.
Referring to FIG. 3, the insulating layer 11 for planarization is etched by a blanket etch-back process or a chemical mechanical polishing (CMP) process until the conductive layer 9, formed over the entire surface of the semiconductor substrate over the sacrificial insulating layer pattern 7, is exposed. After a sputter etching process, a cylindrical storage electrode 9a is formed, remaining only on the side wall and the bottom of the hole exposing the contact plug 5. The inner surface and the outer surface of the vertical pillar for the cylindrical storage electrode 9a are also exposed by removing the insulating layer 11 for planarization remaining inside the storage electrode 9a and the sacrificial insulating layer pattern 7. A high dielectric layer 13 and a plate electrode 15 are sequentially formed over the entire surface of the semiconductor substrate, including the inner surface and the outer surface of the vertical pillar for the cylindrical storage electrode 9a. When the high dielectric layer 13 is formed from either a Ta2O5 layer, a BST layer, a PZT layer, or a PLZT layer, the high dielectric layer 13 must be thermally treated at a temperature of between about 550xc2x0 C. to 750xc2x0 C. to achieve crystallization. During the heat treatment, the grain of the cylindrical storage electrode 9a is grown, so that the cylindrical storage electrode 9a may be easily physically transformed. Such a phenomenon becomes severe as the thickness T2 of the pillar of the cylindrical storage electrode 9a is reduced. As a result, cracks may form in the high dielectric layer 13 due to the physical transformation of the cylindrical storage electrode 9a. 
Accordingly, the cracks which are generated in the high dielectric film degrades the leakage current characteristic of the capacitor and reduces the capacitance. Furthermore, when a pre-treatment process such as a process of cleaning the surface of the cylindrical storage electrode is carried out before forming the high dielectric film, the very thin vertical pillar of the cylindrical storage electrode may be easily broken.
A feature of the present invention is to provide a capacitor having a storage electrode formed from a metal layer or a conductive material layer containing a metal that is resistant to transformation and breakage.
Another feature of the present invention is to provide a method for manufacturing a capacitor, as associated with the first feature of the present invention.
To achieve the first feature of the present invention, there is provided a capacitor comprising a storage electrode having at least two conductive layer patterns. The two conductive layer patterns overlap each other on a semiconductor substrate, and a thermally-stable material layer pattern is positioned between the conductive layer patterns. The conductive layer pattern may consist of a horizontal bottom and a pillar which protrudes upwardly from a predetermined location on the horizontal bottom. Preferably, each conductive layer pattern has a cylindrical shape.
Also, the thermally-stable material layer pattern may be positioned in the entire region between the conductive layer patterns, or may be positioned in the predetermined region between the conductive layer patterns, preferably, only in the region between the pillars of the conductive layer patterns. When the thermally-stable material layer pattern is positioned in the entire region between the conductive layer patterns, the thermally-stable material layer pattern is preferably a conductive layer, that is, a thermally-stable conductive layer. This is because it is possible to maximize the surface area of the storage electrode when the conductive layer patterns, constituting the storage electrode, are electrically connected to each other. However, when the thermally-stable material layer pattern is positioned only between the pillars of the conductive layer patterns and the bottoms of the conductive layer patterns contact each other, the thermally-stable material layer pattern can be formed from a thermally-stable insulating layer or a thermally-stable conductive layer.
When the thermally-stable conductive layer is positioned between the pillars of the conductive layer patterns and the magnitude of the work function of the thermally-stable conductive layer is smaller than that of the intended usage for the conductive layer pattern, the surface height of the thermally-stable conductive layer is preferably lower than the upper surfaces of the pillars. That is, when the required electrical barrier height of the thermally-stable conductive layer is lower than the electrical barrier height of the conductive layer patterns, which form the storage electrode, recessed grooves are preferably formed between the pillars. As a result, the high dielectric layer on the thermally-stable conductive layer is thicker than the high dielectric layer formed on the conductive layer patterns. Accordingly, it is possible to improve a leakage current characteristic between a subsequent plate electrode and the thermally-stable conductive layers, because of the thickness of the high dielectric layer formed on the thermally-stable conductive layer.
Furthermore, the upper portions of the respective pillars may be in contact each other when the thermally-stable material layer pattern is only positioned between the pillars of the respective conductive layer patterns. Accordingly, the thermally-stable material layer pattern is completely surrounded by the respective conductive layer patterns.
The conductive layer pattern is formed from an oxidation-resistant metal layer, such as, either a platinum (Pt) layer, an iridium (Ir) layer, a ruthenium (Ru) layer, or an osmium (Os) layer, or a conductive metal oxide layer such as a ruthenium oxide (RuO2) layer or an iridium oxide (IrO2) layer.
The thermally-stable conductive layer is preferably either a refractory metal layer, a binary refractory metal nitride layer, a ternary refractory metal nitride layer, a refractory metal silicide layer, a conductive carbide layer, or a conductive boride layer. Specifically, the refractory metal layer is preferably a tungsten (W) layer, a titanium (Ti) layer or a tantalum (Ta) layer. The binary refractory metal nitride layer is preferably a TiN layer, a TaN layer, or a WN layer. Also, the ternary refractory metal nitride layer is preferably a WSiN layer, a TiAlN layer, a TiSiN layer, or a TaSiN layer. The refractory metal silicide layer is preferably a TiSi2 layer, a TaSi2 layer, or a WSi2 layer. Also, the conductive carbide layer is preferably a TaC layer, a TiC layer, or a WC layer. The conductive boride layer is preferably a TiB2. The thermally-stable insulating layer is formed from a dielectric layer such as an SiO2 layer, an SiON layer, an Si3N4 layer, an Al2O3 layer, or a Ta2O5, or a dielectric layer having a perovskite structure such as a BST layer, a PZT layer, or a PLZT layer.
To achieve the second feature of the present invention, the method for forming the capacitor comprises the steps of forming a storage electrode having at least two conductive layer patterns which overlap each other on a semiconductor substrate and positioning a thermally-stable material layer between the at least two conductive layer patterns, and sequentially forming a high dielectric layer and a plate electrode on the storage electrode.
The storage electrode and the thermally-stable material layer may be formed by various methods. According to one of the various methods, a sacrificial insulating layer pattern, including a hole which exposes a predetermined region of a semiconductor substrate, is formed on the semiconductor substrate. A conforming conductive layer and a conforming thermally-stable material layer are alternately formed on the resultant pattern. A first material layer and a final material layer must be the conductive layers. Here, the thermally-stable material layer is preferably a material layer having conductivity.
A material layer for planarization by filling a concave region generated by the hole is formed on the final conductive layer. At least two cylindrical conductive layer patterns which overlap each other and thermally-stable material layer patterns positioned between the cylindrical conductive layer patterns are formed inside the hole by performing a sequential blanket etching on the material layer for planarization, the conductive layers, and the thermally-stable material layers, or by sequentially etching the material layer for planarization, the conductive layers, and the thermally-stable material layers using a chemical mechanical polishing (CMP) process, until the sacrificial insulating layer pattern is exposed. The material layer for planarization which resides inside the hole and the sacrificial insulating layer pattern are also removed. As a result, the at least two cylindrical conductive layer patterns form a storage electrode.
A high dielectric layer and a plate electrode are sequentially formed on the entire surface of the resultant structure from which the sacrificial insulating layer pattern was removed. A further step of forming recessed grooves between the cylindrical conductive layer patterns is done by selectively etching the thermally-stable material layer pattern being positioned between the cylindrical conductive layer patterns. At this time, the high dielectric layer must be formed so as to completely fill the grooves.
Furthermore, according to another method of forming the storage electrode and the thermally-stable material layer pattern, a sacrificial insulating layer pattern, including a hole which exposes a predetermined region of a semiconductor substrate, is formed on the semiconductor substrate. A first conforming conductive layer is formed on the sacrificial insulating layer pattern. A thermally-stable material layer is formed over the entire surface of the first conductive layer. A spacer is formed on the side wall of the first conductive material layer by anisotropic-etching the thermally-stable material layer. A second conductive layer is formed over the entire surface, including the area in which the spacer is formed. The first and second conductive layers are preferably formed from the same material layer.
A material layer for planarization fills a concave region generated by the hole that is formed on the second conductive layer. The first and second cylindrical conductive patterns, which overlap each other, are formed inside the hole by performing a sequential blanket etching on the material layer for planarization, the second conductive layer, and the first conductive layer, or by sequentially etching the material layer for planarization, the second conductive layer, and the first conductive layer using a CMP process until the sacrificial insulating layer pattern is exposed. The horizontal bottom of the first cylindrical conductive layer pattern is in contact with the horizontal bottom of the second cylindrical conductive layer pattern, thus being electrically connected to the horizontal bottom of the second cylindrical conductive layer pattern. Therefore, the spacer can be formed of a thermally-stable insulating layer as well as a thermally-stable conductive layer. The material layer for planarization that resides inside the hole and the sacrificial insulating layer pattern are removed, thereby creating first and second cylindrical conductive layer patterns to form a storage electrode.
A high dielectric layer and a plate electrode are sequentially formed over the entire surface of the resulting structure. Here, when the spacer is formed of a thermally-stable conductive layer, a step of forming the recessed grooves between the first and second cylindrical conductive layer pattern is done, by selectively etching the spacer exposed between the first and second cylindrical conductive layer patterns. The high dielectric layer must be formed so as to completely fill the grooves. Also, when the thermally-stable material layer is anisotropic etched, the upper sidewall of the first conductive layer may be exposed by excessively etching the thermally-stable material layer. The upper portion of the pillar of the first cylindrical conductive layer pattern makes contact with the upper portion of the pillar of the second cylindrical conductive pattern. Accordingly, the spacer is completely surrounded by the first and second cylindrical conductive layer patterns.
According to the present invention, a thermally-stable material layer is positioned between at least two conductive layer patterns which form the storage electrode. Therefore, it is possible to prevent the storage electrode from being transformed when a high temperature thermal treatment process is carried out to form the high dielectric layer on the storage electrode or when a subsequent thermal treatment process is performed. Accordingly, it is possible to improve the leakage current characteristic and the reliability of the capacitor since it is possible to prevent the high dielectric layer from being damaged, for example, by cracking.
The above features and advantages of the present invention will become more apparent by referring to the detailed description as set forth in the preferred embodiments of the present invention, with reference to the attached drawings.